An important step in the development of top-gated graphene-based field-effect transistors (FETs) is the growth of high dielectric constant (high-k) materials to act as the gate insulator. For optimal performance, these dielectric thin films should be ultrathin, conformal, and pinhole-free with minimal disorder or traps at the dielectric graphene interface. A very suitable method for controlled deposition of ultrathin homogeneous films is Atomic Layer Deposition (ALD). However, ALD of thin films on graphene is not easy because there is no surface functional group or defect on the inert graphene surface, which are needed for chemical surface reactions the conventional ALD processes are based on.
Several surface treatment methods have been pursued so far to improve the uniformity of gate dielectric growth on graphene by atomic layer deposition (ALD), including the deposition and oxidation of metal films (Fallahazad, B.; Kim, S.; Colombo, L.; Tutuc, E., Dielectric thickness dependence of carrier mobility in graphene with HfO2 top dielectric. Appl Phys Lett 2010, 97 (12)), functionalization of graphene via ozone (Lee, B. K.; Park, S. Y.; Kim, H. C.; Cho, K.; Vogel, E. M.; Kim, M. J.; Wallace, R. M.; Kim, J. Y., Conformal Al2O3 dielectric layer deposited by atomic layer deposition for graphene-based nanoelectronics. Appl Phys Lett 2008, 92 (20)), and the spin-coating of polymer films as seeding layers (Farmer, D. B.; Chiu, H. Y.; Lin, Y. M.; Jenkins, K. A.; Xia, F. N.; Avouris, P., Utilization of a Buffered Dielectric to Achieve High Field-Effect Carrier Mobility in Graphene Transistors. Nano Lett 2009, 9 (12), 4474-4478). Although these methods possess advantages compared to ALD dielectric deposition directly on pristine graphene, important issues remain unresolved. For example, graphene surface pretreatments that involve an oxidizing treatment generally lead to surface damage of the graphene and degradation of its electronic properties. Furthermore, polymer and oxidized metal seeding layers decrease the total capacitance of the gate dielectric layer due to increased gate thickness and a reduced effective k-value.